The present invention relates to a communication system, and more particularly to an input buffer circuit for radio frequency (RF) phase-locked loops(PLLs).
Communication systems for connecting persons to allow them to transmit and receive information back and forth are becoming increasingly powerful. In fact, certain types of systems, such as modems for performing data communication and telephones for performing voice communication, have become indispensable to many users. Generally, communication systems are classified as either wired communication systems which use data transmission lines or wireless communication systems which transmit data using electromagnetic transmissions such as radio frequency (RF) transmissions.
In portable systems that include wireless communication capability, such as pagers, cellular telephones, personal communication service (PCS) phones, personal digital assistants (PDA), and portable computers including laptops and notebook computers, there are several important considerations. These include battery life and, therefore, power consumption, as well as the weight and volume of the system. These factors are all affected by the size and type of integrated circuits that make up the systems in general and their resident communication systems in particular. The size and type of traditionally external components is also an important factor. With the developments made in integrated circuit technology, more and more components which were traditionally considered external components are being embedded in integrated circuits.
FIG. 1 is a block diagram illustrating a conventional communication receiver 100. Referring to FIG. 1, the communication receiver 100 comprises an antenna 1, a speaker 2, a radio frequency (RF) amplifier 10, a mixer 20, an intermediate frequency (IF) amplifier 30, a base band analog processor (BBA) 40, and an RF phase-locked loop (PLL) 95. The PLL 95 includes a voltage-controlled oscillator VCO 50, a frequency divider 75, a phase detector 80 and a filter 90.
The RF amplifier 10 amplifies an RF signal having radio band frequency received from the antenna 1. The mixer 20 mixes the RF signal from the RF amplifier 10 with an oscillating signal generated by the VCO 50 to generate an intermediate frequency (IF) signal having intermediate band frequency. The IF amplifier 30 amplifies the IF signal from the mixer 20. The BBA processor 40 receives the IF signal from the IF amplifier 30 and converts the IF signal to a base band analog (BBA) signal having base band frequency. The BBA signal is provided as an output to the speaker 2.
Generally, phase-locked loops (PLL) can be classified according to their frequency characteristics as radio frequency (RF) phase-locked loops, such as PLL 95 in FIG. 1, and low frequency (LF) PLLs. For example, referring to FIG. 2, which is a detailed block diagram illustrating the RF PLL 95 shown in FIG. 1., recent mobile telecommunication systems such as the cellular phone and the PCS phone use an RF PLL 95 having a prescaler 60 as a principal part of their systems. The LF PLL does not require a prescaler, since the LF PLL is operated at low frequency.
Referring to FIG. 2, the RF PLL 95 comprises the VCO 50, the phase detector 80, the filter 90 and the frequency divider 75, which includes the prescaler 60 and a divider 70. In the RF PLL 95 shown in FIG. 2, the VCO 50 generates an oscillating signal having the radio band frequency. The frequency divider 75 divides the frequency of the oscillating signal from the VCO 50 by a predetermined divisor, for example, N, and outputs a divided oscillating signal Ffeed to the phase detector 80. The prescaler 60 is used for pre-dividing the frequency of the oscillating signal from the VCO 50, and the divider 70 is used for dividing the pre-divided oscillating signal from the prescaler 60.
The prescaler 60 divides the oscillating signal, typically having a frequency in the Gigahertz (GHz) range, and outputs a pre-divided oscillating signal, typically having a frequency in the tens of Megahertz (MHz), to the divider 70. The divider 70 divides the pre-divided oscillating signal and outputs a further divided oscillating signal to the phase detector 80. The prescaler 60 typically includes emitter coupled logic (ECL) circuitry which is applicable for high speed operation.
The phase detector 80 compares a reference input signal Fref having a reference frequency with the divided oscillating signal Ffeed from the frequency divider 75, to generate a control signal which is applied to the VCO 50 through the filter 90, so as to control the VCO 50.
The prescaler 60 composed of the ECL circuitry, comprises an input buffer circuit for amplifying the low-level oscillating signal to the ECL level. The input buffer circuit is capable of operating in the Ghz frequency range and is used to provide a wide input sensitivity to the prescaler 60. One example of the input buffer circuit for the ECL prescaler is set forth in a paper entitled, xe2x80x9cA 3-mW 1.0-Ghz Silicon-ECL Dual-Modulus Prescaler ICxe2x80x9d, by Moriaki Mizuno, Hirokazu Suzuki, Masami Ogawa, Kouji Sato, and Hiromich Ichikawa, published in the December, 1992 issue of IEEE JOURNAL OF SOLID STATE CIRCUITS, vol. 27, No. 12, pages 1794-1797.
FIG. 3 is a circuit diagram which illustrates an input buffer circuit 65 included in the prescaler 60 shown in FIG. 2, and which is disclosed in the above paper. Referring to FIG. 3, the input buffer 65 comprises a first amplifier 61, a second amplifier 62, and a output driving circuit 63. The first amplifier 61 receives an oscillating signal IN and an inverted oscillating signal INB from the VCO 50. The input signals IN and INB have 50 mV-0.5V of peak voltage, and a high frequency response of more than 1 GHz. Transistors Q1, Q2, Q3 and Q4 are included in the first and the second amplifiers 61 and 62. They operate as switches when the voltage of the input signal IN is higher than 100 mV, for example, and operate as amplifiers when the voltage of the input signal IN is 50 mV or less, for example. The bandwidths of output signals OUT and OUTB of the input buffer circuit 65 are restricted by parasitic capacitances existing on nodes N1, N2, N3 and N4, and load resistors RL1, RL2, RL3 and RL4. The output signals OUT and OUTB are digitized by the switching operation of the transistors Q1, Q2, Q3 and Q4, and then they are outputted to the phase detector 80 through the output driving circuit 63.
FIG. 4 is a diagram illustrating simulated output characteristics of the input buffer 65 shown in FIG. 3. The plot of FIG. 4 illustrates a characteristic of the input buffer generated by a computer simulation, such as SPICE, with circuit parameters set as follows: VDD=3V, VBB1=1.5V, RL3=RL4=1.75 kxcexa9, IEE1=IEE2=200 xcexcA, and IEE3=IEE4=50 xcexcA. The simulated frequency response with this current has adequate gain (for example, 14 dB) up to 1.0 Ghz as shown in FIG. 4. The output characteristics of the input buffer 65 will be described in detail below, including comparing them with the output characteristics of an input buffer according to an embodiment of the present invention.
To obtain the output characteristics illustrated in FIG. 4, switching voltages across load resistors RL1, RL2, RL3 and RL4 must be kept above 300 mV in the input buffer circuit 65, so as to satisfy the ECL output characteristics. That is, the first and the second switching voltages obtained by multiplying a first switching current IEE1 and the respective load registers RL1 and RL2 must be kept above 300 mV in the first amplifier 61. Similarly, the third and the fourth switching voltages obtained by multiplying a second switching current IEE2 and the respective load registers RL3 and RL4 must be kept above 300 mV in the second amplifier 62.
Several problems occur in the conventional input buffer circuit 65 in connection with achieving both low power consumption and a wide bandwidth, while satisfying the above described restriction related to the switching voltages. For example, when the resistance of the load resistors RL1, RL2, RL3 and RL4 is reduced, the output bandwidth of the input buffer circuit 65 is enlarged. However, at the same time, the power consumption of the input buffer circuit 65 increases, because the switching currents IEE1 and IEE2 are increased so as to keep the switching voltages above 300 mV. Also, when the switching currents IEE1 and IEE2 are reduced, the power consumption of the input buffer circuit 65 is reduced. But, the output bandwidth of the input buffer circuit 65 becomes narrower because the resistance of the load resistors RL1, RL2, RL3 and RL4 are increased to keep the switching voltages above 300mV.
It is an object of the present invention to provide an input buffer circuit of a prescaler included in an RF PLL, having a wide bandwidth and low power consumption characteristics.
It is another object of the present invention to provide an input buffer circuit capable of controlling its output bandwidth.
In order to attain the above objects, according to an aspect of the present invention, there is provided an input buffer circuit which includes a first switching means having cascode transistors. The first switching means receives a first switching current from a power supply voltage source, switches the first switching current in response to the externally applied oscillating signal, and generates a first and a second switching signal by converting the first switching current into a first and a second switching voltage. A second switching means receives a second switching current from the power supply voltage source and switches the second switching current in response to the first and the second switching signals. A loading means generates a third and a fourth switching signal by converting both the first and the second switching currents into a third and a fourth switching voltage. An output driving means outputs a first and a second output signal in response to the third and the fourth switching signals, respectively.
According to another aspect of this invention, there is provided a cascode circuit having a first and a second resistor used as an equivalent inductance. The output bandwidth of the input buffer circuit can be controlled by the resistors.